We will introduce Verilog-A by showing a number of examples. Each example introduces a new concept or language feature. This is not a definitive reference of the language but we hope to demonstrate the most commonly used features. The table below lists the examples used in this manual along with the path of the files where you can find a read-to-run schematic and Verilog-A definition file.

Example File Location
Hello World! Examples/Verilog-A/Manual/Hello-world
A Simple Device Model Examples/Verilog-A/Manual/Gain-block
A Resistor Examples/Verilog-A/Manual/Resistor
A Soft Limiter Examples/Verilog-A/Manual/Soft-limiter
Hysteresis Block Examples/Verilog-A/Manual/Hysteresis-block
A Capacitor Examples/Verilog-A/Manual/Capacitor
A Voltage Controlled Oscillator Examples/Verilog-A/Manual/Vco
Digital Gate Examples/Verilog-A/Manual/Gates
Butterworth Filter Examples/Verilog-A/Manual/Butterworth-filter
RC Ladder - Loops, Vectored Nodes and genvars Examples/Verilog-A/Manual/RC-ladder
Indirect Assignments Examples/Verilog-A/Manual/Indirect-assignment