SR Latch

In this topic:

Netlist entry

Axxxx s r enable set reset out nout model_name

Connection details

Name Description Flow Type
s S input in d
r R input in d
enable Enable in d
set Asynchronous set in d
reset Asynchronous reset in d
out Data output out d
nout Inverted data output out d

Model format

.MODEL model_name d_srlatch parameters

Model parameters

Name Description Type Default Limits
sr_delay Delay from s or r input change real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
enable_delay Delay from clk real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
set_delay Delay from set real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
reset_delay Delay from reset real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
ic Output initial state integer 0 0 - 2
rise_delay Rise delay real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
fall_delay Fall delay real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
sr_load S & r load values (F) real 1pF none
enable_load Clk load value (F) real 1pF none
set_load Set load value (F) real 1pF none
reset_load Reset load value (F) real 1pF none
family Logic family string UNIV none
in_family Input logic family string UNIV none
out_family Output logic family string UNIV none
out_res Digital output resistance real 100 ???MATH???0 - \infty???MATH???
out_res_pos Digital output res. pos. slope real out_res ???MATH???0 - \infty???MATH???
out_res_neg Digital output res. neg. slope real out_res ???MATH???0 - \infty???MATH???
min_sink Minimum sink current real -0.001 none
max_source Maximum source current real 0.001 none
sink_current Input sink current real 0 none
source_current Input source current real 0 none

Device Operation

This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high.