A Capacitor

To implement a capacitor we need a time derivative function. In Verilog-A this is achieved using the ddt analog operator. A capacitor can be defined using the branch contribution statement:

I(p,n) <+ capacitance * ddt( V(p,n)) ;

Like the resistor, this defines the current/voltage relationship that the simulator must maintain on the nodes p and n. However, this definition has time dependence.

Here is the complete definition for a capacitor:

'include "disciplines.vams"

(* symbol="cap_simple_subckt" *)module va_capacitor(p,n) ;

parameter real capacitance = 1n  ;
electrical p, n ;

I(p,n) <+ capacitance * ddt(V(p,n)) ;


See Examples/Manual/Capacitor. Note there is another definition for a capacitor with an initial condition parameter - capacitor_with_ic.va. This uses the time integration operator idt which allows the specification of an initial condition.