Load Delay

In this topic:


The digital simulator includes mechanisms to model the delay introduced when an output is loaded. Two sources of delay are provided for, namely 'input delay' and 'wire delay'. Input delay is determined by the capacitive input while wire delay is an additional delay caused by the capacitance of the interconnection.

Both input delay and wire delay are affected by the driving outputs 'resistance'.

Output Resistance

Most devices that have digital outputs have three parameters to define output resistance. Note that the resistance we are referring to here is not an actual analog resistance but a conceptual value that when multiplied by load capacitance provides a delay value.

The three output resistance parameters are: out_res, out_res_pos, out_res_neg. out_res_pos and out_res_neg define the output resistance for positive and negative transitions respectively. out_res provides a default value for out_res_pos and out_res_neg.

Input Delay

Most digital inputs include an 'input_load' capacitance parameter. The total input delay is obtained by multiplying the sum of all connected input capacitances by the driving output's output resistance as described above.

Wire Delay

Wire delay is derived from the number of connected inputs following a non-linear relationship defined in a look-up table.

Defining Look-up Table

The wire delay look-up table must be defined in a file containing pairs of values with one pair per line. The first value in the pair is the number of connections and the second is the capacitance. For example:

0 0
1 0
2 1e-12
5 10e-12
10 30e-12

Linear interpolation is used to derive missing values.

To specify the wire table used for a simulation, add the line:

.OPTIONS WireTable=filename

where filename is the path of the wire table file.