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.FILE filename

The .FILE statement allows the contents of a file referenced in a .MODEL statement to be placed directly in the netlist. Files are referenced in arbitrary logic blocks (see Arbitrary Logic Block - User Defined Models), PWLFILE voltage and current sources (see PWL File Source), digital sources (see Digital Signal Source) and digital state machines (see State Machine). Each of these may refer to files defined using .FILE and .ENDF.


.MODEL COUNT_8 d_logic_block file=counter_def

.FILE counter_def
PORT (DELAY = 10n) CountOut out[0:7] ;

EDGE (DELAY=5n, WIDTH=8, CLOCK=in[0]) Count ;

Count = Count + 1 ;

CountOut = count ;

The .MODEL statement refers to a file called 'counter_def'. This could be a real disk file called counter_def or counter_def.ldf, but in the above example it is instead defined directly in the netlist using .FILE and .ENDF.

Important Note

.FILE and .ENDF will not be recognised in library files.

Using with SIMPLIS

When using .FILE and .ENDF with the SIMPLIS simulator, the text "SIMPLIS_PASS_THRU" must be placed at the end of the .FILE statement: