Defining Verilog-A Files in Netlist

Use the simulator statement '.LOAD' to specify the Verilog-A source file. E.g.:


This will invoke the Verilog-A compiler (va.exe) which will create one common 'C' file and one 'C' file per module statement within the Verilog-A file. The 'C' files will then be compiled and linked using gcc to produce the final DLL which has the extension .sxdev. These files are all placed in the directory %APPDATAPATH%\SIMetrixvvv\vacache where %APPDATAPATH% is your application data directory. (vvv is the product version, e.g. 830 for version 8.3)

Having compiled the va file, .LOAD will load the .sxdev file into the SIMetrix memory image. It will then map the code within into the simulator's model table making the new device ready for use.

To use the new device or devices, defined with Verilog-A module statements, you must specify a .MODEL statement. These must be placed after the .LOAD statement. The format of the .MODEL statement should be:

.MODEL modelname va-mod-name parameters

Where modelname is the model name referred to on the instance (see below), va-mod-name is the name of the module in the Verilog-A source file and parameters are parameters defined using the Verilog-A parameter keyword.

To create instances of the new device create an instance line (or schematic symbol with appropriate properties) that begins with one of the letters 'N', 'P', 'W', 'U' or 'Y'. You can use other letters as long as the number of terminals is compatible with the original use of that letter. For example, you can use the letter 'M' as long as the device has four terminals - as a MOS device would have. But you must use one of 'N', 'P', 'W', 'U' or 'Y' for devices with more than 4 terminals or only a single terminal. We recommend you avoid using 'Q'; this device can 3 or 4 terminals which can lead to some ambiguities.

When you start a new simulation, any sxdev files loaded in the previous run will be unloaded and the model table entries removed.