***
*** line_and_load_regulation.testplan
***
*?@ analysis	objective	source	load	label	postprocess
SteadyState	SteadyState	SOURCE(INPUT:1, Minimum)	LOAD(OUTPUT:1, 100%)	Steady-State|Input 1 Minimum Voltage, Output 1 100% Load
SteadyState	SteadyState	SOURCE(INPUT:1, Maximum)	LOAD(OUTPUT:1, Light)	Steady-State|Input 1 Maximum Voltage, Output 1 Light Load
SteadyState	SteadyState	SOURCE(INPUT:1, Nominal)	LOAD(OUTPUT:1, 100%)	Steady-State|Input 1 Nominal Voltage, Output 1 100% Load
SteadyState	SteadyState	SOURCE(INPUT:1, Nominal)	LOAD(OUTPUT:1, Light)	Steady-State|Input 1 Nominal Voltage, Output 1 Light Load
SteadyState	SteadyState	SOURCE(INPUT:1, Minimum)	LOAD(OUTPUT:1, 50%)	Steady-State|Input 1 Minimum Voltage, Output 1 50% Load
SteadyState	SteadyState	SOURCE(INPUT:1, Maximum)	LOAD(OUTPUT:1, 50%)	Steady-State|Input 1 Maximum Voltage, Output 1 50% Load
NoSimulation	NoSimulation			Final Math	simplis_dvm_advanced_testplan_line_and_load_regulation_post_process